{"id":72360,"date":"2018-02-07T09:45:59","date_gmt":"2018-02-07T09:45:59","guid":{"rendered":"https:\/\/qantur.com\/?page_id=72360"},"modified":"2018-02-23T06:49:04","modified_gmt":"2018-02-23T06:49:04","slug":"ansys-pathfinder","status":"publish","type":"page","link":"https:\/\/qantur.com\/ansys-pathfinder\/","title":{"rendered":"ANSYS PathFinder"},"content":{"rendered":"<p>[vc_row type=&#8221;container&#8221; padding_top=&#8221;&#8221; padding_bottom=&#8221;&#8221; css=&#8221;.vc_custom_1449576470084{margin-bottom: 0px !important;}&#8221;][vc_column width=&#8221;1\/2&#8243;][vc_column_text]ANSYS PathFinder helps you plan, verify and sign-off IP and full-chip SoC designs for integrity and robustness against electrostatic discharge (ESD). The analysis is performed at the layout and circuit levels to help you identify and isolate design issues that can cause chip or IP failure from charged-device model (CDM), human body model (HBM) or other ESD events.<\/p>\n<p>Using layout and circuit-level analysis you can identify and isolate design issues that can cause chip or IP failure due to charged-device model (CDM), human body model (HBM) or other ESD events.[\/vc_column_text][\/vc_column][vc_column width=&#8221;1\/2&#8243;][vc_single_image image=&#8221;72724&#8243; img_size=&#8221;full&#8221; add_caption=&#8221;yes&#8221;][\/vc_column][\/vc_row][vc_row type=&#8221;container&#8221; padding_top=&#8221;&#8221; padding_bottom=&#8221;&#8221; css=&#8221;.vc_custom_1444503683289{margin-bottom: 0px !important;}&#8221;][vc_column][vc_separator color=&#8221;#e2e2e2&#8243; type=&#8221;normal&#8221; thickness=&#8221;1&#8243; up=&#8221;&#8221; down=&#8221;&#8221; el_class=&#8221;dotted&#8221;][\/vc_column][\/vc_row][vc_row type=&#8221;container&#8221; padding_top=&#8221;&#8221; padding_bottom=&#8221;&#8221;][vc_column][vc_column_text]<\/p>\n<h2>More About ANSYS PathFinder<\/h2>\n<ul>\n<li style=\"margin-bottom: 15px;\">PathFinder is certified by a number of foundries as an ESD sign-off solution, giving you the assurance that the interconnect parasitic extraction, HBM\/CDM ESD simulation and current-density checks on ESD discharge paths are accurate by foundry standards.<\/li>\n<li>PathFinder offers layout-based analysis and a GUI for detecting layout issues that could lead to ESD events.<\/li>\n<\/ul>\n<p>[\/vc_column_text][\/vc_column][\/vc_row][vc_row type=&#8221;container&#8221; padding_top=&#8221;&#8221; padding_bottom=&#8221;&#8221; css=&#8221;.vc_custom_1444503683289{margin-bottom: 0px !important;}&#8221;][vc_column][vc_separator color=&#8221;#e2e2e2&#8243; type=&#8221;normal&#8221; thickness=&#8221;1&#8243; up=&#8221;&#8221; down=&#8221;&#8221; el_class=&#8221;dotted&#8221;][\/vc_column][\/vc_row][vc_row type=&#8221;container&#8221; padding_top=&#8221;&#8221; padding_bottom=&#8221;&#8221;][vc_column][vc_column_text]<\/p>\n<h2>Capabilities of ANSYS PathFinder<\/h2>\n<p>Electrostatic discharge integrity: IP to SoC[\/vc_column_text][\/vc_column][\/vc_row][vc_row type=&#8221;container&#8221;][vc_column width=&#8221;1\/2&#8243;][vc_tta_accordion style=&#8221;flat&#8221; c_icon=&#8221;&#8221; active_section=&#8221;0&#8243; collapsible_all=&#8221;true&#8221;][vc_tta_section title=&#8221;HBM\/CDM ESD Events&#8221; tab_id=&#8221;1517229416690-e3b46802-1048&#8243;][vc_column_text]PathFinder provides you with comprehensive coverage of on-chip ESD events, which is a requirement for most chip designs.[\/vc_column_text][\/vc_tta_section][\/vc_tta_accordion][vc_tta_accordion style=&#8221;flat&#8221; c_icon=&#8221;&#8221; active_section=&#8221;0&#8243; collapsible_all=&#8221;true&#8221; el_class=&#8221;.content-area h4{ font-size: 16px; }&#8221;][vc_tta_section title=&#8221;SINGLE PASS SIMULATION AND RESULTS ANALYSIS&#8221; tab_id=&#8221;1517229414199-0c9b2857-778d&#8221;][vc_column_text]PathFinder\u2019s integrated data modeling, extraction and simulation engine offer you an end-to end-solution for ESD verification.[\/vc_column_text][\/vc_tta_section][\/vc_tta_accordion][vc_tta_accordion style=&#8221;flat&#8221; c_icon=&#8221;&#8221; active_section=&#8221;0&#8243; collapsible_all=&#8221;true&#8221;][vc_tta_section title=&#8221;LAYOUT-BASED ANALYSIS AND ROOT CAUSE DETECTION&#8221; tab_id=&#8221;1517229417043-140239e0-acb4&#8243;][vc_column_text]RedHawk offers you the capacity and performance to simulate designs having over 1 billion instances using advanced Distributed Machine Processing (DMP) techniques.[\/vc_column_text][\/vc_tta_section][\/vc_tta_accordion][\/vc_column][vc_column width=&#8221;1\/2&#8243;][vc_tta_accordion style=&#8221;flat&#8221; c_icon=&#8221;&#8221; active_section=&#8221;0&#8243; collapsible_all=&#8221;true&#8221;][vc_tta_section title=&#8221;SILICON-CORRELATED ACCURACY&#8221; tab_id=&#8221;1517229415645-560c4ab5-19e0&#8243;][vc_column_text]Increasing current densities in advanced technologies lead to more ESD issues. PathFinder provides accurate ESD analysis prior to sign-off to ensure first-time silicon success.[\/vc_column_text][\/vc_tta_section][\/vc_tta_accordion][vc_tta_accordion style=&#8221;flat&#8221; c_icon=&#8221;&#8221; active_section=&#8221;0&#8243; collapsible_all=&#8221;true&#8221;][vc_tta_section title=&#8221;CAPACITY AND PERFORMANCE&#8221; tab_id=&#8221;1517229415988-be78e28a-6cb6&#8243;][vc_column_text]With distributed computing, PathFinder can simultaneously handle hundreds of domains in one analysis for faster turnaround.[\/vc_column_text][\/vc_tta_section][\/vc_tta_accordion][vc_tta_accordion style=&#8221;flat&#8221; c_icon=&#8221;&#8221; active_section=&#8221;0&#8243; collapsible_all=&#8221;true&#8221;][vc_tta_section title=&#8221;LIBRARY TO SOC-LEVEL ESD INTEGRITY&#8221; tab_id=&#8221;1517229416352-c3f21fc6-3a59&#8243;][vc_column_text]PathFinder offers you the coverage, accuracy, capacity and performance to address ESD issues from standard cell to SoC levels of design.[\/vc_column_text][\/vc_tta_section][\/vc_tta_accordion][\/vc_column][\/vc_row][vc_row type=&#8221;container&#8221;][vc_column][vc_empty_space][\/vc_column][\/vc_row]<\/p>\n","protected":false},"excerpt":{"rendered":"<p>[vc_row type=&#8221;container&#8221; padding_top=&#8221;&#8221; padding_bottom=&#8221;&#8221; css=&#8221;.vc_custom_1449576470084{margin-bottom: 0px !important;}&#8221;][vc_column width=&#8221;1\/2&#8243;][vc_column_text]ANSYS PathFinder helps you plan, verify and sign-off IP and full-chip SoC designs for integrity and robustness against electrostatic discharge (ESD). The analysis is performed at the layout and circuit levels to help you identify and isolate design issues that can cause chip or IP failure from charged-device&hellip;<\/p>\n","protected":false},"author":1,"featured_media":71925,"parent":0,"menu_order":1,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"acf":[],"_links":{"self":[{"href":"https:\/\/qantur.com\/wp-json\/wp\/v2\/pages\/72360"}],"collection":[{"href":"https:\/\/qantur.com\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/qantur.com\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/qantur.com\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/qantur.com\/wp-json\/wp\/v2\/comments?post=72360"}],"version-history":[{"count":9,"href":"https:\/\/qantur.com\/wp-json\/wp\/v2\/pages\/72360\/revisions"}],"predecessor-version":[{"id":73246,"href":"https:\/\/qantur.com\/wp-json\/wp\/v2\/pages\/72360\/revisions\/73246"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/qantur.com\/wp-json\/wp\/v2\/media\/71925"}],"wp:attachment":[{"href":"https:\/\/qantur.com\/wp-json\/wp\/v2\/media?parent=72360"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}