ANSYS PowerArtist is the comprehensive design-for- power platform of choice of all leading low-power semiconductor design companies for early RTL power analysis and reduction. PowerArtist enables you to perform physical-aware RTL power budgeting, interactive debugging, analysis-driven reduction, efficiency regressions and profiling of live applications, while also enabling a seamless RTL-to- physical methodology for power grid integrity.
ANSYS PowerArtist to analyze and reduce power early in the development cycle for the highest impact.
More About ANSYS PowerArtist
- PowerArtist automatically identifies block and instance-level sequential and combinational power reduction opportunities across clock network, data path and memory architectures to meet aggressive power targets.
- Using a powerful interactive graphical debug environment, RTL designers (especially those new to power) can easily and efficiently debug power hotspots
- PowerArtist’s clock gating and power efficiency metrics and TCL interface for custom queries enable rigorous tracking of power through regression methodologies.
Capabilities of ANSYS PowerArtist
PowerArtist provides industry’s fastest power profiling capability, which can analyze activity of live applications comprising tens of milliseconds within hours — several orders of magnitude faster than traditional approaches.
Make reliable design decisions early with unique PowerArtist PACE™ technology that models physical effects, such as clock distribution, for consistent RTL power numbers versus post-layout.
Identify power hotspots and quickly debug their root cause with an intuitive graphical interface and custom queries into the database with a powerful Tcl interface.
Generate RTL power profiles of system application-level activity scenarios, such as OS boot up, orders of magnitude faster, and avoid late and costly surprises.
Reduce clock, memory and logic power with high-impact block-level and instance-level RTL techniques based on production-proven foundation power analysis technology.
Perform early power grid prototyping and increase sign-off coverage by focusing on peak and di/dt cycles rapidly located by PowerArtist RTL Power Model, and used by ANSYS RedHawk directly.
Prevent power creep through regular and rigorous monitoring of power and power efficiency metrics throughout your design development cycle.