ANSYS Totem is a transistor-level power noise and reliability simulation platform that enables you to meet increasingly stringent power and reliability requirements for IPs, analog, mixed-signal and custom digital designs. Totem enables design analysis while taking package and substrate parasitics into account, with SPICE-level accuracy.

As the signoff platform for all foundries down to 7nm, Totem helps you meet stringent power noise and reliability requirements for your IPs, analog and custom IC designs.


More About ANSYS Totem

  • Totem is the only solution today that can natively analyze complex mixed-signal IP blocks that have both analog and digital content.
  • Totem offers SPICE-level accuracy while taking package and substrate parasitics into account for power noise and thermal-aware EM analyses.

Features of ANSYS Totem

Industry-proven and foundry-certified analog and mixed-signal EM/IR solution.

Total enables you to identify and mitigate power noise and reliability issues of multigigabit SerDes IPs.

Using Totem’s multifunctional GUI, you can overlay simulation results on your layout and perform interactive root cause analysis and what-if fixing to accelerate design cycles.

ANSYS Totem is the industry’s only analog and mixed-signal power integrity and reliability solution with a proven silicon track record.

Power management is a key component of practically every electronic IC and system. With Totem, you can analyze and identify design weaknesses of PMICs.

Totem’s silicon-correlated substrate analysis helps you assess the noise impact on timing, frequency domain analysis and quality of the guard ring.

Totem helps you sign off on your analog and mixed-signal IPs, and embed and verify SoC integration constraints such as connectivity limits, voltage drop thresholds and rules.