ANSYS RedHawk is an industry standard power noise and reliability sign-off solution for your SoC designs. With a track record of thousands of designs in silicon, RedHawk enables you to create high-performance SoCs that are still power efficient and reliable against thermal, electromigration (EM) and electrostatic discharge (ESD) issues for markets such as mobile, communications.

Redhawk has been the go-to sign-off solution for all foundries and processes since 2006, enabling you to create robust, low-power, high-performance SoCs in the most advanced FinFET technology.


More About ANSYS RedHawk

  • RedHawk’s advanced Distributed Machine Processing (DMP) enables significantly higher capacity and better performance for full-chip IR/dynamic voltage drop, power/signal electromigration (EM) and electrostatic discharge (ESD) analyses.
  • RedHawk’s complete and accurate model-based interoperability with ANSYS board and system-level tools ensures that your chip works as intended in the system.

Capabilities of ANSYS RedHawk

The capabilities of ANSYS RedHawk help create robust, low-power, high-performance SoCs, including the ones using the most advanced sub-16 nm FinFETs and 3-D ICs.

Chip-package- system co-analysis provides superior simulation accuracy and greater design insight than current independent analyses of chip and package.

RedHawk offers you the capacity and performance to simulate designs having over 1 billion instances using advanced Distributed Machine Processing (DMP) techniques.

Encapsulating chips within a 2.5-D or 3-D package improves power, performance and form factor. Redhawk is qualified for the 2.5-D and 3-D package reference flows.

Redhawk identifies thermal integrity and thermal-aware reliability issues, which can have a significant impact on power (leakage), IR, timing and electromigration (EM), especially in automobile applications.

Provides foundry-certified accuracy for the reduced noise margins and higher voltage drops typical for FinFET designs.

RedHawk helps you understand the impact of dynamic voltage drop on timing for clock and critical paths using full-chip- level timing-impact analysis in a SPICE-based sign-off simulation.